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PRELIMINARY
CY28412
Clock Generator for Intel(R) Grantsdale Chipset
Features
* Supports Intel P4 and Prescott CPU * Selectable CPU frequencies * Differential CPU clock pairs * 100 MHz differential SRC clocks * 96 MHz differential dot clock * 48 MHz USB clocks * 33 MHz PCI clock CPU x2 / x3 SRC x7 / x8 PCI x8 REF x2 DOT96 x1 USB_48 x1 * Low-voltage frequency select input * I2C Support with read back capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin SSOP package
Block Diagram
XIN XOUT CPU_STP# PCI_STP# FS_[C:A] VTT_PWRGD# IREF
Pin Configuration
PCI0 PCI1 VDD_PCI VDD_CPU GND_PCI CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI2 VDD_SRC PCI3 SRCT[0:6], SRCC[0:6], PCI4 SATA[T/C] PCI5 GND_PCI VDD_PCI VDD_PCI TEST_SEL/PCIF0 PCI[0:5] ITP_EN/PCIF1 VDD_PCIF PCIF[0:1] VDD_48 USB48/FS_B GND_48 VDD_48 MHz DOT96T DOT96T DOT96C DOT96C VTT_PwrGd#/PD USB_48 SRCT0 SRCC0 SRCT1 STCC1 VDD_SRC GND_SRC SRCT2 SRCC2 SATAT SATAC
VDD_REF REF[1:0]
XTAL OSC PLL1
PLL Ref Freq
Divider Network
PD
PLL2
SDATA SCLK
I2C Logic
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDD_REF REF0/FS_C REF1/FS_A GND_REF X1 X2 SDATA SCLK GND_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF GND_A VDD_A CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 VDD_SRC SRCT5 SRCC5 GND_SRC SRCT4 SRCC4 SRCT3 SRCC3 VDD_SRC
56 SSOP
CY28412
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
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www.SpectraLinear.com
CY28412
Pin Definitions
Pin No. 47,46,44,43 39,38 CPUT/C CPUT2_ITP/SRCT6, CPUC2_ITP/SRCC6 DOT96T, DOT96C REF0/FS_C, REF1/FS_A USB48/FS_B Name Type O, DIF Differential CPU clock outputs. O, DIF Selectable Differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC6 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Fixed 96-MHz clock output. I/O 14.318-MHz reference clock/3.3V-tolerant input for CPU frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. Fixed 48-MHz USB clock output/3.3V-tolerant input for CPU frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. A precision resistor is attached to this pin, which is connected to the internal current reference. Free-running 33-MHz clocks/ 3.3V-tolerant input for selecting test mode. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD 1 = All outputs are three-stated for test 0 = All outputs normal operation **This input has an internal pull-down resistor. Description
16,17 55, 54
14
I/O
42 1,2,5,6,7,8 11
IREF PCI[0:5] TEST_SEL/PCIF0
I
O, SE 33-MHz clocks. I/O
12
ITP_EN/PCIF1
I/O, SE Free-running 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC6 I I/O SMBus-compatible SCLOCK. SMBus-compatible SDATA.
49 50 27,28
SCLK SDATA SATAT, SATAC
O, DIF Differential serial reference clock. Recommended output for SATA. O, DIF Differential serial reference clocks.
19,20,21,22, SRCT/C[0:5] 25,26,30,31, 32,33,35,36 13 45 3,10 56 23,29,37 40 15 48 4,9 53 24,34 41 18 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDD_A GND_48 GND_CPU GND_PCI GND_REF GND_SRC GND_A VTT_PWRGD#/PD
PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND I, PU
3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for PLL. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for PLL. 3.3V LVTTL input is a level sensitive strobe used to latch the REF0/FSC, REF1/FSA, USB48/FSB, TEST_SEL/PCIF0 and ITP_EN/PCIF1 inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for asserting power-down (active HIGH). 14.318-MHz crystal input.
52 51
X1 X2
I
O, SE 14.318-MHz crystal output.
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CY28412
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B and FS_C input values. For all logic levels of FS_A, FS_B and FS_C VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B and FS_C transitions will be ignored, except in test mode. izes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialTable 1. Frequency Select Table (FS_A, FS_B, FS_C) FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100 MHz 133 MHz 166 MHz 200 MHz 266 MHz 333 MHz 400 MHz Reserved SRC 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
PCIF/PCI 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
DOT96 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz
USB 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz
Table 2. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from master Block Read Protocol Description
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Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit .... .... .... .... .... .... ...................... Data Byte (N - 1) - 8 bits Acknowledge from slave Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 39:46 47 48:55 56 .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop Byte Read Protocol Description Block Read Protocol Description Data byte from slave - 8 bits Acknowledge from master Data byte from slave - 8 bits Acknowledge from master Data byte N from slave - 8 bits Acknowledge from master Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Control Registers
Byte 0:Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SATAT/C] SRC[T/C]2 SRC[T/C]1 SRC[T/C]0 Description CPU[T/C]2_ITP/SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SATA[T/C] Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable
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CY28412
Byte 1: Control Register 1 Bit 7 @Pup 1 Name CPUT/C SRCT/C PCIF PCI DOT_96T/C USB_48 REF0 REF1 CPU[T/C]1 CPU[T/C]0 CPUT/C SRCT/C PCIF PCI Description Center Spread Enable 0 = 0.25% Center Spread, 1 = -0.5% Down Spread
6 5 4 3 2 1 0
1 1 1 1 1 1 0
DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled REF1 Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 PCIF1 PCIF0 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled PCIF0 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 3: Control Register 3 Bit 7 6 5 4 3 @Pup 0 0 0 0 0 Name CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SATA[T/C] Description Allow control of SRC[T/C]6 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]5with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]3with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of SATA[T/C] with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP#
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CY28412
Byte 3: Control Register 3 (continued) Bit 2 1 0 @Pup 0 0 0 Name SRC2 SRC1 SRC0 Description Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of SRC[T/C]0 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP#
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name RESERVED DOT96[T/C] PCIF1 PCIF0 RESERVED RESERVED RESERVED RESERVED RESERVED, Set = 0 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z Allow control of PCIF2 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# RESERVED, Set = 0 RESERVED, Set = 1 RESERVED, Set = 1 RESERVED, Set = 1 Description
Byte 5: Control Register 5 Bit 7 @Pup 0 Name Description SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C]Stop Drive Mode 0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted RESERVED RESERVED RESERVED RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0
6 5 4 3 2 1 0
0 0 0 0 0 0 0
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted
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CY28412
Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 1 1 1 REF1 REF0 PCIF, SRC, PCI Name RESERVED RESERVED, Set = 0 Test Clock Mode Entry Control 1 = Hi-Z mode, 0 = Normal operation REF1 Output Drive Strength 0 = Low, 1 = High REF0 Output Drive Strength 0 = Low, 1 = High SW PCI_STP# Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. FS_C. Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during VTT_PWRGD# assertion FS_B. Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during VTT_PWRGD# assertion FS_A. Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during VTT_PWRGD# assertion Description
2 1 0
Externally selected Externally selected Externally selected
CPUT/C CPUT/C CPUT/C
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Crystal Recommendations
The CY28412 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28412 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm
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CY28412
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be 2 times the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks are driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) - Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must be held high or Hi-Z (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock output must be held with "Diff clock" pin driven high at 2 x Iref, and "Diff clock#" tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are Hi-Z. Note the example below shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,166,200,266,333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 s after asserting VTT_PWRGD#.
=
1 ( Ce1 + Cs1 + Ci1
+
1
1 Ce2 + Cs2 + Ci2
)
CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs ............................................. Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.)
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CY28412
clock chip. All differential outputs stopped in a tristate condition resulting from power down must be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each other.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the
Clock Chip
Ci1
Ci2 Pin 3 to 6p
Cs1
X1
X2
Cs2 Trace 2.8pF
XTAL Ce1
Ce2
Trim 33pF
Figure 2. Crystal Loading Example
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF
Figure 3. Power-down Assertion Timing Waveform Rev 1.0, November 20, 2006 Page 9 of 16
CY28412
Below is an example showing the relationship of clocks coming up.
Tstable <1.8ms
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300 S, >200mV
Figure 4. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
W ait for VTT_PW RGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PW RGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 5. VTT_PWRGD# Timing Diagram
S1 S2 VTT_PW R G D# = Low
D elay >0.25m S
VDD _A = 2.0V
S am ple Inputs straps
W ait for <1.8m s S0 S3 VD D_A = off
P ow er O ff
N orm al O peration
VTT_PW RG D # = toggle
Enable O utputs
Figure 6. Clock Generator Power-up/Run State Diagram
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CY28412
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 70 150 31.89 48.29 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description 3.3 5% Condition Min. 3.135 Max. 3.465 Unit V 3.3V Operating Voltage VDD_A, VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU VILI2C VIHI2C VIL_FS VIH_FS VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPD3.3V Input Low Voltage Input High Voltage FS_(A,B,C) Input Low Voltage FS_(A,B,C) Input High Voltage Input Low Voltage Input High Voltage Input Low Leakage Current Input High Leakage Current Output Low Voltage Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max load and freq per Figure 8 PD asserted, Outputs driven PD asserted, Outputs Hi-Z except internal pull-up resistors, 0 < VIN < VDD except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA - 2.4 -10 2 3 - 0.7VDD 0 - - -
SDATA, SCLK SDATA, SCLK
- 2.2 VSS - 0.3 0.7 VSS - 0.5 2.0 -5
1.0 - 0.35 VDD + 0.5 0.8 VDD + 0.5 5 0.4 - 10 5 6 7 VDD 0.3VDD 500 75 2
V V V V V V A A V V A pF pF nH V V mA mA mA
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AC Electrical Specifications
Parameter Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1- s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX 47.5 69.841 - - - 45 9.9970 7.4978 5.9982 4.9985 3.7489 2.9991 2.4993 9.9970 7.4978 5.9982 4.9985 3.7489 2.9991 2.4993 - - - - 175 - - - Math averages Figure 8 Math averages Figure 8 660 -150 250 - -0.3 See Figure 8. Measure SE Measured at crossing point VOX Measured at crossing point VOX - 45 9.9970 9.9970 52.5 71.0 10.0 500 300 55 10.003 7.5023 6.0018 5.0015 3.7511 3.0009 2.5008 10.0533 7.5400 6.0320 5.0266 3.7700 3.0160 2.5133 100 85 125 150 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 10.003 10.0533 % ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps ps % ps ps mv mv mv V V V % ns ns Description Condition Min. Max. Unit
TPERIOD T R / TF TCCJ LACC TDC TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100 MHz CPUT and CPUC Period 133 MHz CPUT and CPUC Period 166 MHz CPUT and CPUC Period 200 MHz CPUT and CPUC Period 266 MHz CPUT and CPUC Period 333 MHz CPUT and CPUC Period 400 MHz CPUT and CPUC Period
CPU at 0.7V
TPERIODSS 100 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 133 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 166 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 200 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 266 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 333 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 400 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TSKEW TCCJ TCCJ2 TSKEW2 T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB SRC TDC TPERIOD SRCT and SRCC Duty Cycle 100 MHz SRCT and SRCC Period Any CPUT/C to CPUT/C Clock Skew, SSC CPUT/C Cycle to Cycle Jitter CPU2_ITP Cycle to Cycle Jitter CPU2_ITP to CPU0 Clock Skew CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
TPERIODSS 100 MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
Rev 1.0, November 20, 2006
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CY28412
AC Electrical Specifications (continued)
Parameter TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB TSKEW PCI/PCIF TDC TPERIOD TPERIOD THIGH TLOW T R / TF TSKEW TCCJ DOT TDC TPERIOD TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB USB TDC TPERIOD THIGH TLOW Duty Cycle Period USB high time USB low time Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V 45 20.8271 8.094 7.694 55 20.8396 10.036 9.836 % ns ns ns DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy DOT96T and DOT96C Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage See Figure 8. Measure SE Math averages Figure 8 Math averages Figure 8 Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) 45 10.4135 - - 175 - - - 660 -150 250 - -0.3 - 55 10.4198 250 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 % ns ps ppm ps % ps ps mv mv mV V V V PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Enabled PCIF/PCI Period PCIF and PCI high time PCIF and PCI low time PCIF and PCI Edge Rate Any PCI clock to Any PCI clock Skew PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V 45 29.9910 29.9910 12.0 12.0 0.5 - - 55 30.0090 30.1598 - - 2.0 500 500 % ns ns ns ns V/ns ps ps Description SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Any SRCT/C to SRCT/C Clock Skew See Figure 8. Measure SE Measured at Crossing point VOX Math averages Figure 8 Math averages Figure 8 Condition Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. - - 175 - - - 660 -150 250 - -0.3 - - Max. 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 250 Unit ps ppm ps % ps ps mv mv mV V V V ps
Rev 1.0, November 20, 2006
Page 13 of 16
CY28412
AC Electrical Specifications (continued)
Parameter T R / TF TCCJ REF TDC TPERIOD T R / TF TCCJ TSTABLE TSS TSH REF Duty Cycle REF Period REF Edge Rate REF Cycle to Cycle Jitter Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V 45 69.8203 0.5 - - 10.0 0 55 69.8622 2.0 1000 1.8 - - % ns V/ns ps ms ns ns Description USB Edge Rate USB Cycle to Cycle Jitter Condition Measured between 0.8V and 2.0V Measurement at 1.5V Min. 1.0 - Max. 2.0 350 Unit V/ns ps
ENABLE/DISABLE and SETUP
Test and Measurement Set-up
For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals.
Measurement Point PCI/ USB
4pF
Measurement Point
4pF
Measurement Point
4pF
REF
Measurement Point
4pF
Measurement Point
4pF
Figure 7. Single-ended Load Configuration
Rev 1.0, November 20, 2006
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CY28412
For Differential CPU, SRC and DOT96 Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs.
CPUT SRCT D O T96T CPUC SRCC D O T96C IR E F
M e a s u re m e n t P o in t
2pF
D if f e r e n t ia l
M e a s u re m e n t P o in t
2pF
Figure 8. 0.7V Single-ended Load Configuration
3 .3 V s ig n a l s
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 9. Single-ended Output Signals (for AC Parameters Measurement)
Rev 1.0, November 20, 2006
Page 15 of 16
CY28412
Ordering Information
Part Number Standard Package Type Product Flow
CY28412OC CY28412OCT
Lead-free
56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin SSOP 56-pin SSOP - Tape and Reel
Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
CY28412OXC CY28412OXCT
Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 16 of 16

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